Empower Innovation at IDEAS 2023 Digital Forum
Empower Innovation at IDEAS 2023 Digital Forum
IDEAS is an exciting and enriching platform for professionals in the field of chips, photonics, and electronics design. Listen to the innovative ideas and state-of-the-art experiences of your colleagues in the industry that have resulted in successful tapeouts.
Who Should Attend
Ansys virtual user conference for electronics, semiconductors and photonics designers.
Time: 16.00 CEST
Agenda
| TIME PST | TITLE | SPEAKER(S) |
|---|---|---|
| 08:00 AM 08:15 AM |
Opening Keynote
|
Prith Banerjee
Chief Technology Officer, Ansys
|
| 08:15 AM 08:45 AM |
Keynote
|
Lalitha Immaneni
Vice President, Intel
|
| 08:45 AM 09:15 AM |
Technology Keynote
|
|
| 09:15 AM 09:45 AM |
SigmaDVD: The Solution to the Transient Coverage Problem
|
Chip Stratakos
Microsoft
|
| 09:15 AM 09:45 AM |
Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
|
Matthew Jastrzebski
Engineer, Intel Corporation
|
| 09:15 AM 09:45 AM |
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
|
Alexander Pivovarov
SMTS, AMD
|
| 09:15 AM 09:45 AM |
Laying the Foundations for Optical Pass-Through Links’ Design
|
Luca Ramini
Research Scientist, Hewlett Packard Labs
|
| 09:15 AM 09:45 AM |
Revolutionizing Chip Design: Python-Powered Workflow with Gdsfactory and Lumerical-Ansys Integration”
|
Joaquin Matres
Photonics Engineer, Google X
|
| 09:15 AM 09:45 AM |
A Multiphysics Simulation Flow for High Performance MMIC Products for 5G and RF Applications
|
Vittorio Cuoco
Senior Principal Modeling Engineer – Multiphysics Simulations Competence Manager, Ampelon
|
| 09:15 AM 09:45 AM |
A Novel Methodology for EM/IR analysis of Complex LDO/Power Gated Designs
|
Pavan Bilekallu
Lead Engineer, Layout, Qualcomm India Pvt. Ltd.
|
| 09:15 AM 09:45 AM |
Accuracy and Performance benchmarks for Gate-level Power Integrity Signoff with RedHawk-SC Advanced Power Analytics
|
Love Gupta
Principal Design Engineer, NXP
|
| 09:45 AM 10:15 AM |
Early IR Drop Prediction Using Machine Learning for Power Grid
|
Anil D’Souza
CAD Engineer, Intel Technology Pvt Ltd
|
| 09:45 AM 10:15 AM |
A Virtual Prototyping System for Silicon Carbide Power Modules
|
James Victory
Fellow, onsemi
|
| 09:45 AM 10:15 AM |
Simulation Driven Enhancements to Photonic Integrated Circuit Devices in Tower’s PH18 Platform
|
Bowen Wang
Sr Staff, Tower Semiconductor
|
| 09:45 AM 10:15 AM |
SigmaDVD: High Coverage Solution for Power Integrity Signoff
|
Anusha Vemuri
Physical Design Methodology Engineer, NVIDIA
|
| 09:45 AM 10:15 AM |
A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
|
Ping Ding
Backend Designeer, Sanechips
|
| 09:45 AM 10:15 AM |
Tracking Power Trends and Optimizations using PowerArtist and Actual Graphics Workloads
|
Sandesh Saokar
Graphics Hardware Engineer, Intel
|
| 09:45 AM 10:15 AM |
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
|
Marc Swinnen
Senior Principal Product Marketing Manager, Ansys
Keith Lanier
Technical Product Mgmt Director, Synopsys
|
| 09:45 AM 10:15 AM |
Leveraging Scan Vectorless for ATPG Robustness
|
Mohit Jain
Principal Engineer, Qualcomm
|
| 09:45 AM 10:15 AM |
Thermal Aware Vectorless EM/IR Sign-off for Custom-IPs
|
Ayan Roy Chowdhury
Engineering Manager, Intel Technology India
|
| 10:15 AM 10:45 AM |
EMA3D Charge
|
Timothy McDonald
President, EMA
|
| 10:15 AM 10:45 AM |
EPDA: Bringing Layout Awareness to Photonics Simulation
|
Gilles LAMANT
Distinguished Engineer, Cadence Design Systems Inc
|
| 10:15 AM 10:45 AM |
Optimizing Ansys Redhawk-SC with AMD Over InfiniBand Interconnect
|
Andy Chan
Lead, Microsoft Semiconductor Community, Microsoft
|
| 10:15 AM 10:45 AM |
Early Clock Tree Power Correlation at SOC: A Case Study
|
Sri Sai Pavan Pasumarthi
Senior Engineer, Qualcomm
|
| 10:15 AM 10:45 AM |
Silicon Interposer Extraction Using Ansys RaptorX
|
Garth Sundberg
Senior Principal Engineer, Ansys
|
| 10:15 AM 10:45 AM |
SPICE Validation of Dynamic Voltage Drops from SigmaDVD
|
Andy Hoover
Senior Principal Technologist
|
| 10:15 AM 10:45 AM |
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
|
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
|
| 10:45 AM 11:15 AM |
Novel Hierarchical IREM Sign-off Flow Using ROM
|
Dongyoun Yi
Staff Engineer, Samsung Electronics
|
| 10:45 AM 11:15 AM |
Innovating Semiconductor Design with Ansys applications on AWS
|
Dnyanesh Digraskar
Principal HPC Partner Solutions Architect, AWS
|
| 10:45 AM 11:15 AM |
3DIC Compiler & RHSC ET
|
|
| 10:45 AM 11:15 AM |
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
|
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
|
| 10:45 AM 11:15 AM |
Integrated IR Shift-Left Solution in Construction in Fusion Compiler’s RedHawk Analysis Fusion (RAF)
|
Kiran Adhikari
Hardware Engineer, Microsoft Corporation
|
| 11:15 AM 11:45 AM |
3DIC Compiler & RHSC ET
|
|
| 11:15 AM 11:45 AM |
Aggressor Aware Design for Improved IR-Drop Results
|
Vlad Berlin
Physical Design Engineer, Retym
|
| 11:15 AM 11:45 AM |
The tool certification process of Ansys RedHawk-SC Electrothermal: another successful collaboration with Ansys
|
Ki Wook Jung
Staff Engineer, Foundry Business, Samsung Electronics
|
